Projects
Scalable Asynchronous AER Circuit Design
Studied and implemented asynchronous AER circuits for neuromorphic communication. Designed mask-based arbitration logic and dual-level architecture to reduce latency and area. Verified via Verilog and FPGA (Basys-3).
FPGA-Based Image Processing System
Developed RTL modules for image memory (BRAM), address generation, and VGA controller. Implemented enhancements like grayscale conversion and thresholding. Deployed on hardware for real-time display.
Schematic and Layout Design of CMOS
Designed and simulated basic digital blocks (Inverter, Flip-Flops, Logic Gates) using Cadence Virtuoso at 180nm technology. Performed DRC, LVS, and area estimation.
FSM-Based Automatic Vending Machine
Designed an automatic vending system using Verilog based on FSM modeling. Accepted coin denominations, developed logic for product dispensing and invalid input handling in Vivado.